Defect classification should be a solved problem.
It isn't. We're fixing that.
How Wafertune started
Jonas Falk spent five years building wafer defect analysis tools in a computational imaging research group before founding Wafertune. The work was technically interesting — convolutional models trained on spatial die-map data, spatial feature extraction pipelines, probability calibration for classification confidence. But the applications were research prototypes, not production tools.
The core observation was straightforward: defect pattern recognition is a computer vision problem. The semiconductor industry had been solving it by hand — process engineers visually reviewing wafer map printouts, categorizing patterns based on experience — in 2023. The problem wasn't unsolvable. It was unsolved at production scale for specialty fabs because the training data didn't exist in the right form.
Wafertune was founded in Phoenix in 2024 to productize an ML approach trained specifically on specialty-node defect data. Phoenix was a deliberate choice: proximity to TSMC Arizona's expanding fabs, Intel's Ocotillo campus, ON Semiconductor, and Microchip Technology gave direct access to the specialty fab ecosystem where the product needed to prove itself.
Four people, based in Phoenix.
ML engineers and semiconductor specialists. We combine computer vision background with real fab-floor process experience.
Computational imaging research, defect analysis tooling. Built the core classification model architecture.
Computer vision specialist, previously at Synopsys EDA. Spatial feature extraction and model training pipelines.
Analog process engineering background from Intel Ocotillo. Defect physics domain expert and taxonomy lead.
Data engineering background from Microchip Technology. Builds the API infrastructure and STDF processing pipeline.
From research to product
We're hiring engineers who want to solve real manufacturing problems.
Small team. Hard problem. Phoenix-based or remote.
Get in touch