The Team.
ML engineers and semiconductor specialists, based in Phoenix.
Team members
Computational imaging and ML background. Five years building wafer defect analysis tools before starting Wafertune. Designed the classification model architecture.
Computer vision specialist, previously on the EDA verification ML team at Synopsys. Leads spatial feature extraction, model training pipelines, and confidence calibration.
Analog process engineering experience from Intel Ocotillo. Deep understanding of 200mm BiCMOS and analog CMOS defect mechanisms. Leads taxonomy definition and model validation.
Data engineering background from Microchip Technology's data platform team. Builds and maintains the API infrastructure, STDF processing pipeline, and classification latency monitoring.
"We're looking for engineers who are curious about both the ML and the manufacturing sides. The interesting problems are at the intersection."
Jonas Falk, Founder — We're a small team. If you want to work on hard problems in a domain where ML is still genuinely novel, talk to us.